Hardware System Builder
Fast track your HDL development beyond vendor IDEs
Organize your HDL IP on a validated graph, generate the top-level interconnect, simulate and build locally, and let LLM agents drive the toolchain over MCP.
Architecture
Loose IP in, working system out
Drop your existing HDL IP blocks on the graph. HSB checks types, widths and bus groups, then generates the top-level interconnect file: a scalable, readable way to build a programmable system on FPGA families that lack Intel QSYS or AMD Vivado.
Editing & simulation
Editing, simulation, waveforms: integrated
VHDL and Verilog with tree-sitter parsing, completion, formatting and linting. GHDL and Icarus flows with testbench discovery, and a fast integrated VCD waveform viewer.
Automation
An MCP server for LLM agents
The built-in MCP server exposes inspection, graph surgery, simulation and vendor builds, so an agent can drive the whole toolchain headlessly.
Beyond vendor IDEs
Efinix integration is available today, and the vendor layer is a clean interface. Your flow is not tied to one toolchain.
Yours to keep
Pro Annual keeps perpetual rights to every covered release. Projects stay readable forever, even in Viewer mode.
Local first
Builds, simulation and project files stay on your machine. The cloud only handles licensing and downloads.
Start with the free Viewer
Inspect any project for free. Full tool from €9/month. Perpetual rights with Pro Annual.